DocumentCode
3215837
Title
A test synthesis technique using redundant register transfers
Author
Papachristou, C. ; Baklashov, M.
Author_Institution
Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA
fYear
1997
fDate
9-13 Nov. 1997
Firstpage
414
Lastpage
420
Abstract
This paper presents a test synthesis technique for behavioral descriptions. The technique is guided by two testability metrics which quantify the controllability and observability of behavioral variables and structural signals. The method is based on utilizing redundant register transfers in the data path to produce a test behavior with better controllability and observability properties. This approach can avoid unnecessary insertions of test structures in the data path. A test scheme for conditional statements has been developed involving minimal changes in the controller. Our experimental results show improvements in fault coverage at modest hardware overhead.
Keywords
automatic testing; built-in self test; directed graphs; hardware description languages; high level synthesis; logic testing; redundancy; VHDL; behavioral descriptions; behavioral variables; conditional statements; controllability; data path; fault coverage; graph theory; hardware overhead; high level synthesis; observability; redundant register transfers; structural signals; test synthesis technique; testability metrics; Logic circuit testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1997. Digest of Technical Papers., 1997 IEEE/ACM International Conference on
Conference_Location
San Jose, CA, USA
ISSN
1092-3152
Print_ISBN
0-8186-8200-0
Type
conf
DOI
10.1109/ICCAD.1997.643569
Filename
643569
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