DocumentCode
3219523
Title
1-bit sub threshold full adders in 65nm CMOS technology
Author
Moradi, Farshad ; Wisland, Dag T. ; Cao, Tuan Vu ; Peiravi, Ali ; Mahmoodi, Hamid
Author_Institution
Dept. of Inf., Univ. of Oslo, Oslo, Norway
fYear
2008
fDate
14-17 Dec. 2008
Firstpage
268
Lastpage
271
Abstract
In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results show a 5%-20% for frequency ranges from 1 KHz to 20 MHz and supply voltages lower than 0.3 V.
Keywords
CMOS integrated circuits; adders; logic gates; CMOS technology; frequency 1 kHz to 20 MHz; full adder circuit; modified XOR gates; size 65 nm; subthreshold region; ultra low power operation; word length 1 bit; Adders; CMOS technology; Circuit simulation; Circuit topology; Delay; Dynamic voltage scaling; Energy consumption; Low voltage; MOS devices; Threshold voltage; Full adder; subthreshold; ultra low power;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics, 2008. ICM 2008. International Conference on
Conference_Location
Sharjah
Print_ISBN
978-1-4244-2369-9
Electronic_ISBN
978-1-4244-2370-5
Type
conf
DOI
10.1109/ICM.2008.5393820
Filename
5393820
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