Multiple-junction surface tunnel transistors for multiple-valued logic circuits

Multiple-junction surface tunnel transistors (MJ-STTs), in which gate-controlled multiple p^-/n^- tunnel-junctions are connected in series between the source and drain, are proposed for application as multiple-valued logic circuits. The transistor operation with four negative-differential-resistance characteristics is confirmed by fabricating a GaAs-based four-tunnel-junction MJ-STT. In addition, to demonstrate the increased functionality of these MJ-STTs, a tri-stable circuit is constructed with an MJ-STT and a load resistor connected in series. Three output voltages (states) are controlled by a reset pulse and successive input pulses applied to the gate of the MJ-STT, confirming the success of the tri-stable operation