DocumentCode
3220657
Title
An approach to diagnose logical faults in partially observable sequential circuits
Author
Yamazaki, Koji ; Yamada, Teruhiko
Author_Institution
Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan
fYear
1997
fDate
17-19 Nov 1997
Firstpage
168
Lastpage
173
Abstract
We propose an approach for locating logical faults in sequential circuits under the condition that all the internal nets are not observable. In this approach, candidates for the error sources are first deduced by an error propagation traceback starting from the failing primary outputs. Then, with the aid of probing, the possible error sources are found. Simulation results for ISCAS´89 benchmark circuits show that a reasonable diagnostic resolution can be achieved by our approach if more than 50% of the internal nets are observable
Keywords
VLSI; circuit analysis computing; digital simulation; fault diagnosis; logic testing; sequential circuits; ISCAS´89 benchmark circuits; diagnostic resolution; error propagation traceback; error sources; failing primary outputs; internal nets; logical faults; partially observable sequential circuits; probing; simulation results; Circuit faults; Circuit simulation; Circuit testing; Computer errors; Computer science; Costs; Error correction; Fault diagnosis; Flip-flops; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1997. (ATS '97) Proceedings., Sixth Asian
Conference_Location
Akita
ISSN
1081-7735
Print_ISBN
0-8186-8209-4
Type
conf
DOI
10.1109/ATS.1997.643954
Filename
643954
Link To Document