DocumentCode
3222577
Title
Correlation of silicon wafer strength to the surface morphology
Author
Omar, Ghazali ; Tamaldin, Noreffendy ; Muhamad, Muhamad Rasat ; Hock, Tan Chong
Author_Institution
ON Semicond., Senawang, Malaysia
fYear
2000
fDate
2000
Firstpage
147
Lastpage
151
Abstract
The trend in microelectronic packaging is towards thinner and smaller packages. To achieve this, the die must be smaller and thinner as well, which means greater susceptibility to process related failures, especially in the front-end processes. Silicon strength has been recognized as an important parameter in wafer processing, packaging and die assembly due to process-induced stresses. The strength of the silicon wafer is heavily dependent on how the backside surface is prepared prior to metal deposition. Flaws such as small microcracks or etch pits can occur during backside processes, causing the strength of the silicon to decrease, leading to fracture. This paper investigates the effect of die strength on the surface morphology using a ball breaker test and atomic force microscopy (AFM). The die strength was characterized using the ball breaker test while surface morphology was characterized using AFM. The methodologies of the ball breaker test and AFM were documented. The evaluation was performed for wafers with wet etch, smooth grind and rough grind types of backside surface finish. It shows that wet etched wafers have the highest strength and rough grind have the lowest
Keywords
atomic force microscopy; crystal morphology; elemental semiconductors; fracture; integrated circuit packaging; integrated circuit testing; internal stresses; mechanical strength; mechanical testing; microassembling; microcracks; silicon; surface topography; AFM; atomic force microscopy; backside processes; backside surface preparation; ball breaker test; die assembly; die size; die strength; etch pits; fracture; front-end processes; metal deposition; microcracks; microelectronic packaging; package size; packaging; process related failures; process-induced stresses; rough grind backside surface finish; silicon strength; silicon wafer; silicon wafer strength; smooth grind backside surface finish; surface morphology; wafer processing; wet etch backside surface finish; Atomic force microscopy; Microelectronics; Packaging; Rough surfaces; Silicon; Surface cracks; Surface morphology; Surface roughness; Testing; Wet etching;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2000. Proceedings. ICSE 2000. IEEE International Conference on
Conference_Location
Guoman Port Dickson Resort
Print_ISBN
0-7803-6430-9
Type
conf
DOI
10.1109/SMELEC.2000.932453
Filename
932453
Link To Document