Drain induced barrier lowering (DIBL) accurate model for nanoscale Si-MOSFET transistor

Author

Al-Mistarihi, Mamoun F. ; Rjoub, Abdoul ; Al-Taradeh, Nedal R.

Author_Institution

Electr. Eng. Dept., Jordan Univ. of Sci. & Technol., Irbid, Jordan

fYear

2013

fDate

15-18 Dec. 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, an accurate new model for drain induced barrier lowering (DIBL) tunneling in silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) is proposed. The effect of drain (V_ds) and substrate (V_bs) voltages variation on DIBL is discussed. The dependency of channel length variation (ΔL), junction depth (r_j), and substrate impurity concentration (N_B) on DIBL is analyzed, and new equations are obtained. The evaluation results for the proposed model using MATHEMATICA give good agreement when compared with analytical and simulation results for BSIM4 level 54 and recent well-known models using HSPICE simulator.

Keywords

MOSFET; elemental semiconductors; nanoelectronics; semiconductor device models; silicon; silicon-on-insulator; tunnel transistors; BSIM4 level 54; DIBL; HSPICE simulator; Mathematica; SOI; Si; channel length variation dependency; drain induced barrier lowering accurate model; drain induced barrier lowering tunneling; junction depth; nanoscale silicon-MOSFET transistor; silicon on insulator metal oxide semiconductor field effect transistor; substrate impurity concentration; substrate voltage variation; Analytical models; Logic gates; Niobium; Semiconductor device modeling; Junction depth (rj); channel length variation (ΔL); drain induced barrier lowering (DIBL); metal oxide semiconductor field effect transistor (MOSFET); silicon on insulator (SOI); substrate impurity concentration (NB);

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics (ICM), 2013 25th International Conference on

Conference_Location

Beirut

Print_ISBN

978-1-4799-3569-7

Type

conf

DOI

10.1109/ICM.2013.6735011

Filename

6735011