Dynamic Re-Configuration Model for System-On-Chip Design for Test and Testability

The more and more increased complexity of the modern VLSI chips, along with the integration of analogue and digital parts in the same chip, implies a proportionally equivalent rise of the costs involved in design for testability. The paper presents a new method for designing test procedures inside system-on-chip cores aiming to reduce the related costs and to increase the quality of production. The new proposed structure for testing is based on the re-configurability feature of the SoC devices and will rely in the next scenario: the core provider will design a testing configuration stored somewhere on chip (it will steal only 10% of the on-chip flash memory), the user configuration (the active one) will be loaded over the testing configuration (which is enabled) allowing user to include it\´s own testing procedures inside it. As a result, the testing configuration will waste no resources from the designer\´s point of view. When tested, the SoC will "morph " in the TESTING mode and will allow full testing procedures accordingly to standards. When returning to the \´normal\´ mode, the SoC will regain its full functionality, hiding the test configuration and freeing-up the resources for designer\´s use