Simulation study on field-plated buried gate-buried channel SiC MESFETs

Author

Zhang, Rui ; Lu, Hongliang ; Zhang, Yimen ; Zhang, Yuming

Author_Institution

Key Lab. of Wide Band-Gap Semicond. Mater. & Devices, Xidian Univ., Xi´´an, China

fYear

2009

fDate

25-27 Dec. 2009

Firstpage

487

Lastpage

490

Abstract

4H-SiC metal-semiconductor field effect transistors (MESFETs) with field-plated (FP) and buried gate-buried channel structures are proposed and simulated. The buried gate-buried channel structure serves to reduce the surface trapping effects, and the field-plated structure acts as to increase the breakdown voltage and reduce the peak electric field at the edge of the gate and drain side. The small signal AC performance of this kind of MESFETs is also enhanced with the increment of the length of the FP.

Keywords

Schottky gate field effect transistors; electric breakdown; silicon compounds; wide band gap semiconductors; SiC; breakdown voltage; buried gate-buried channel structures; electric field; field-plated buried gate-buried channel SiC MESFET; metal-semiconductor field effect transistors; surface trapping effects; Breakdown voltage; Buffer layers; Doping; Electric breakdown; FETs; Integrated circuit modeling; MESFETs; Samarium; Silicon carbide; Thermal conductivity; AC small-signal; Breakdown; Buried Gate-Buried Channel; DC; Field-Plated; MESFET;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2009. EDSSC 2009. IEEE International Conference of

Conference_Location

Xi´an

Print_ISBN

978-1-4244-4297-3

Electronic_ISBN

978-1-4244-4298-0

Type

conf

DOI

10.1109/EDSSC.2009.5394208

Filename

5394208