Characterization and modeling of electrical stresses on digital integrated circuits power integrity and conducted emission

Author

Boyer, A. ; Ben Dhia, S.

Author_Institution

INSA, Univ. de Toulouse; UPS, Toulouse, France

fYear

2013

fDate

15-18 Dec. 2013

Firstpage

190

Lastpage

195

Abstract

Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity and the conducted emission of digital integrated circuits, clarifying the origin of electromagnetic emission evolution and proposing a methodology to predict this evolution. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip and conducted emission measurements are combined with electric stress to characterize the influence of aging. Simulations based on ICEM modeling modified by an empirical coefficient to model the evolution of the emission induced by device aging is proposed and tested.

Keywords

CMOS digital integrated circuits; integrated circuit modelling; microprocessor chips; power supply circuits; CMOS technology; ICEM modeling; conducted emission; digital integrated circuits; electrical stresses; electromagnetic emission; integrated circuit aging; on-chip measurements; power integrity; power supply voltage; size 90 nm; Degradation; Integrated circuit modeling; Power supplies; Stress; Stress measurement; Voltage measurement; ICEM modelling; Integrated circuits; accelerated aging; conducted emission; power integrity;

fLanguage

English

Publisher

ieee

Conference_Titel

Electromagnetic Compatibility of Integrated Circuits (EMC Compo), 2013 9th Intl Workshop on

Conference_Location

Nara

Type

conf

DOI

10.1109/EMCCompo.2013.6735199

Filename

6735199