A 9T subthreshold SRAM bitcell with data-independent bitline leakage for improved bitline swing and variation tolerance

This paper describes a 9T SRAM bitcell with data-independent bitline leakage for improving bitline voltage swing and variation tolerance. The data-independent bitline leakage eliminates the bitline voltage swing dependency on column data and demonstrates better variation tolerance. Simulations show that the proposed SRAM bitcell enables 1024 cells to be attached in a bitline with the swing of 141mV at a 0.25V and 80°C condition. The proposed cell lowers the minimum operating voltage from 0.3V to 0.15V with 256cells/bitline. It has an area overhead of 5.5%.