A 10-bit 1.25GSample/s partially-segmented D/A Converter for Ultra Wide-Band communication system

Author

Cho, Soon-Ik ; Lim, Shin-Il ; Kim, Suki

Author_Institution

Sch. of Electr. Eng., Korea Univ., Seoul, South Korea

fYear

2010

fDate

6-9 Dec. 2010

Firstpage

378

Lastpage

381

Abstract

This paper proposes a 10-bit 1.25GSample/s partially-segmented D/A converter for Ultra Wide-Band communication system fabricated in a digital 0.18um 1-poly 6-metal standard CMOS technology. To achieve low power consumption and small chip area with good linearity we employ partially segmented D/A converter architecture. Also, we use deglitch circuit and common-centroid layout scheme in the current cell matrix to obtain good linearity of the converter. Simulation results show that the implemented D/A converter has 73dB SFDR at 426MHz input signal with 49.5mW power consumption. The maximum integral nonlinearity (INL) is 0.3LSB and the maximum differential nonlinearity (DNL) is 0.15LSB. The active chip area is 2.21mm².

Keywords

CMOS analogue integrated circuits; digital-analogue conversion; integrated circuit layout; low-power electronics; matrix algebra; ultra wideband communication; DNL; INL; SFDR; common-centroid layout scheme; current cell matrix; deglitch circuit; frequency 426 MHz; low power consumption; maximum differential nonlinearity; maximum integral nonlinearity; partially segmented D/A converter architecture; partially-segmented D/A converter; power 49.5 mW; size 0.18 mum; standard CMOS technology; ultra wide-band communication system; word length 10 bit; CMOS integrated circuits; CMOS technology; Decoding; Latches; Common-centroid current cell matrix; DAC; Deglitch circuit; Digital-to-Analog Converter; Partially-Segmented; Ultra Wide-Band;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (APCCAS), 2010 IEEE Asia Pacific Conference on

Conference_Location

Kuala Lumpur

Print_ISBN

978-1-4244-7454-7

Type

conf

DOI

10.1109/APCCAS.2010.5774966

Filename

5774966