Power consumption & reliability in NanoCMOS

Thermal issues is an important challenge in NanoCMOS chips. High temperatures can reduce the reliability, so it is important to reduce power consumption to improve reliability. It is necessary a change in physical design paradigms to reduce the needed amount of transistors to perform one task. This work shows a new approach to reduce the amount of transistors by using complex gates and a new set of EDA tools to generate any transistor network. Some results show an important reduction on power consumption, improving also circuit reliability.