Estimation-based run-time power profile flattening for RF-powered smart card systems

Power-constrained systems, such as RF-powered smart cards are gaining increased significance in the embedded system´s domain. These systems are highly susceptible to supply voltage drops caused by power peak regions that impact on the system stability. Power profile flattening mechanisms have emerged as an effective power peak countermeasure to enhance system reliability. In this paper we present a hardware power profile flattening approach by employing system-level DVFS adaptions coupled with a hardware power estimation architecture. The exploitation of hardware-accelerated real-time power estimation techniques replaces costly analog on-chip power measurements and enables the dynamic control of the system´s power consumption in a purely digital manner. We demonstrate the effectiveness of our approach by conducting power profiling and voltage drop analysis of a deep-submicron RF-powered smart card system.