Design and simulation of logic circuits by combined single-electron/MOS Transistor Structures

Based on both the I-V characteristics of single-electron transistors and the MOS digital integrated circuit design concept, a good combination of single-electron transistors with MOS transistors is advanced to create a novel inverter, which, compared with the pure SET circuit, is considerably augmented in its voltage gain and drive capability. Then a close analysis was conducted of the inverter, on the basis of which other logic gates were presented. These logic gates are applied to the half adder circuit and the odd-even checker. The accuracy of two circuits is verified through the test on SPICE. The simulated result shows that these hybrid circuits share the merits with both SET circuits and MOS circuits. Compared with the traditional circuits, the two combinational logic circuits use fewer electronic components and are lower in power dissipation.