A test methodology for determining space-readiness of Xilinx SRAM-based FPGA designs

Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an very active area of research for the past decade. Since both the circuit and the circuitpsilas state are stored in radiation-tolerant memory, both could be altered by the harsh space radiation environment. Both the circuit and the circuitpsilas state can be protected by triple-modular redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and modeling. While accelerator testing is the current ldquogold standardrdquo for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors earlier in the design process.