Physical and electrical characterization and optimization of mesa isolation for 0.35/0.25 μm SOI

Due to the compressive thinning of the gate oxide and the two dimensional field effects at the top corner of the transistor, there are two problems that SOI shares with bulk: lowering of the threshold voltage and GOI degradation. The V_t lowering can produce excessive off current and GOI degradation impairs reliability. The focus of this paper is on V_t degradation. One approach to solving this problem is to increase the radius of curvature of the top corner. By properly targeting the sidewall/corner oxide thickness and increasing the HCl content in the oxidizing species, a substantially larger radius of curvature for the mesa/trench corner can be obtained. Additional improvement is obtained with the use of a sidewall implant to further increase the V_t of the corner transistor. Although RTO yields the largest radius of curvature, its process cost is not favorable