• DocumentCode
    3235926
  • Title

    Exploiting ghost-FSMs as a BIST structure for sequential machines

  • Author

    Roy, S. ; Maulik, U. ; Sikdar, Biplab K.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Kalyani Gov. Eng. Coll., India
  • fYear
    2003
  • fDate
    4-8 Jan. 2003
  • Firstpage
    155
  • Lastpage
    160
  • Abstract
    This paper introduces the novel concept of ghost-FSM as a BIST structure for sequential machines. A ghost-FSM is a contrived implicit machine that is deliberately embedded within the framework of a given FSM. A ghost-FSM remains dormant except at the testing phase, when it helps to generate those test patterns that, otherwise, could not be generated due to certain idiosyncrasies of finite state machines. It acts as an effective tool to enhance the fault coverage of a sequential machine in a PRPG based BIST environment, without affecting the normal operating mode of the machine. Extensive experimentation, carried out on MCNC benchmarks, confirm that significant improvement in testability is attained with occasional, very little, area overhead.
  • Keywords
    VLSI; automatic test pattern generation; built-in self test; finite state machines; logic testing; sequential machines; BIST structure; PRPG based BIST environment; area overhead; contrived implicit machine; fault coverage; ghost-FSMs; pseudo random pattern generators; sequential machines; test patterns; testability; testing phase; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Combinational circuits; Computer science; Flip-flops; Sequential circuits; Strontium; Test pattern generators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 2003. Proceedings. 16th International Conference on
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-1868-0
  • Type

    conf

  • DOI
    10.1109/ICVD.2003.1183130
  • Filename
    1183130