DocumentCode

3236969

Title

Designing Testable Plas for both Offline Testing and Concurrent Error Detection

Author

Sharma, Rajiv ; Rajashekhara, T.N.

Author_Institution

Dept. of Electrical & Computer Engineering, University of Wisconsin

fYear

1987

fDate

31896

Firstpage

64

Lastpage

68

Keywords

Clocks; Decoding; Fault detection; Hardware; Programmable logic arrays; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Southern Tier Technical Conference, 1987. Proceedings of the 1987 IEEE

Type

conf

DOI

10.1109/STIER.1987.716381

Filename

716381