Implementation of Low Power Finite Impulse Response Primitive Operator Filters on FPGAs

This paper describes the implementation of a low power Finite Impulse Response (FIR) primitive operator filter (POF) using a Xilinx XC2VP30 field programmable gate array (FPGA). The filter was compared with a standard FIR filter that used the FPGA´s internal multipliers. It was shown that the POF technique gave a modest power reduction, while filtering a 4 kHz signal, of 4.8 mW compared to the standard implementation.