• DocumentCode
    3239519
  • Title

    ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis

  • Author

    Li, Duo ; Tan, Sheldon X D ; McGaughy, Bruce

  • Author_Institution
    Dept. of Electr. Eng., Univ. of California, Riverside, Riverside, CA
  • fYear
    2008
  • fDate
    10-14 March 2008
  • Firstpage
    432
  • Lastpage
    437
  • Abstract
    In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model order reduction techniques to reduce the before the simulation. Different from the (improved) extended Krylov subspace methods EKS/IEKS [15, 2], ETBR performs fast truncated balanced realization on response Grammian to reduce the original system with the similar computation costs of EKS. ETBR also avoids the adverse explicit moment representation of the input signals. Instead, it uses spectrum representation of input signals by fast Fourier transformation. As a result, ETBR is more flexible for different types of input sources and can better capture the high frequency contents than EKS, and this leads to more accurate results especially for fast changing input signals. Experimental results on a number of large networks (up to one million nodes) show that, given the same order of the reduced model, ETBR is indeed more accurate than the EKS method especially for input sources rich in high-frequency components. ETBR also shows similar computation costs of EKS and less memory consumption than EKS.
  • Keywords
    fast Fourier transforms; matrix algebra; power grids; power system simulation; reduced order systems; ETBR; circuit matrix; extended truncated balanced realization method; fast Fourier transformation; on-chip power grid network analysis; response Grammian; spectrum representation; Circuit simulation; Computational efficiency; Computational modeling; Degradation; Frequency; Integrated circuit interconnections; Network-on-a-chip; Power grids; Taylor series; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation and Test in Europe, 2008. DATE '08
  • Conference_Location
    Munich
  • Print_ISBN
    978-3-9810801-3-1
  • Electronic_ISBN
    978-3-9810801-4-8
  • Type

    conf

  • DOI
    10.1109/DATE.2008.4484719
  • Filename
    4484719