Peak power minimization through datapath scheduling

In this paper, we describe new integer linear programming models and algorithms for datapath scheduling that aim at minimizing peak power while maintaining performance. The first algorithm, MVDFC combines both multiple supply voltages and dynamic frequency clocking for peak power reduction, while the second algorithm, MVMC explores multiple supply voltages and multicycling. The algorithms use the number and type of different functional units at different operating voltages as the resource constraints. The effectiveness of the proposed scheduling algorithms is studied by estimating the peak power consumption and the power delay product (PDP) of the datapath circuit being synthesised. The algorithms have been applied to various high level synthesis benchmark circuits under different resource constraints. Experimental results show that for the MVDFC, under various resource constraints using two supply voltage levels (5.0V, 3.3V), average peak power reduction around 75% and average PDP reduction of 60% can be obtained. For the MVMC scheme, average peak power reduction is around 36% and average PDP reduction is 20%, for similar resource constraints.