Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges

Future system design methodologies must accept the fact that the underlying hardware will be imperfect, and enable design of robust systems that are resilient to hardware imperfections. Three techniques that can enable a sea change in robust system design are: 1. built-in soft error resilience (BISER), 2. circuit failure prediction, and 3. concurrent autonomous self-test using stored patterns (CASP). Global optimization across multiple abstraction layers is essential for cost-effective robust system design using these techniques.