Flexible CPLDs for low pin-count applications

Author

Barnett, Ed

fYear

1995

fDate

7-9 Nov. 1995

Firstpage

206

Abstract

ICT Inc offers the most flexible PLD solutions for lower pin-count applications. ICT´s Programmable Electrically Erasable Logic PEEL products include PEEL devices, PEEL Arrays and PEEL Development Tools. The PEEL product features include the most extensive PLD architecture offering in 20-44 pin packages. The technology is CMOS electrically erasable logic. The product line is a direct “JEDEC file-compatible” replacement and a super-set for the popular PAL´s, GAL´s and EPLD´s. The product line offers flexible architectures with extended logic for new designs or design enhancements. The product pin-to-pin speeds are characterized to 5 ns and faster, ICT Inc. offers a broad variety of packaging options. The products are available in DIP, PLCC, SOIC and TSSOP packages. ICT Inc. offers advanced development software for PEEL arrays and PEEL devices. This includes the PEEL architectural compiler, architectural editing, logic compilation, multi-level logic simulation and translation of standard PLD´s to PEEL products. The programmer interfaces to ICT´s proprietary PDS-3 as well as industry standard third party programmers

Keywords

CMOS logic circuits; CMOS technology; Clocks; Computer architecture; Logic arrays; Logic design; Logic devices; Packaging; Programmable logic arrays; Programming profession;

fLanguage

English

Publisher

ieee

Conference_Titel

WESCON/'95. Conference record. 'Microelectronics Communications Technology Producing Quality Products Mobile and Portable Power Emerging Technologies'

Conference_Location

San Francisco, CA, USA

ISSN

1095-791X

Print_ISBN

0-7803-2636-9

Type

conf

DOI

10.1109/WESCON.1995.485278

Filename

485278