PCI bus master in a QuickLogic 8000 gate FPGA

This paper describes the major components of a PCI Master/Slave Interface implemented in a QuickLogic 8000 gate FPGA. The design as implemented interfaces with a Ethernet microcontroller. It can be easily modified to support other back-end devices. The QuickWorks design entry package (from QuickLogic) was used to enter the design. This design package includes schematic and HDL entry, synthesis, place and route, and simulation tools. Its true benefit is the ability to use the most appropriate design entry methods (schematics, HDL) for any part of a design. The Verilog simulator included in the package allows very comprehensive simulation environments to be created. Which can test a design both before and after layout. The methodology used in this design will allow modification with relative ease. As the back end interface is changed, the test fixture can be modified to emulate the back-end device being implemented. The complicated work involving the PCI Bus Interface and its testing has been completed, easing the load for the design engineer with a tight time budget