An SBus Multi Tracer and its applications

An SBus Multi Tracer (MT) is described, which is based on our previously developed SBus monitoring board (SMB), which can provide timing diagrams for all SBus signals. However, just like any other logic analyzer or a bus analyzer its trace length is limited by the board memory and it is difficult to cope with multi occurrences of trigger patterns in a single application. An effective answer to this problem is to design an SBus Multi Tracer instead of increasing the size of the board memory. An SMB with MT achieves multiple partitions of its tracing memory by tracing a fixed number of events after each trigger. In this way it provides systematic timing information for a series of pattern occurrences in a sequence of system operations. The possible operation of the SMB is enabled by a built-in Field Programmable Gate Array (FPGA) chip, which has access to all SBus signals, and can easily be reconfigured to provide additional triggering patterns