Singular value decomposition on distributed reconfigurable systems

The use of FPGAs (field programmable gate arrays) in the area of rapid prototyping and reconfigurable computing has been successful in the past. Although many experiments have shown FPGAs to be faster than general-purpose processors and more flexible than ASICs (application-specific integrated circuits) on some classes of problems, few experiments have offered a computing platform which exploits the reconfigurability aspect of FPGAs and combines FPGAs and processors to provide better solutions on applications. This paper shows, through an efficient implementation of the singular value decomposition (SVD) of very large matrices, the possibility of integrating FPGAs as part of a distributed reconfigurable system (DRS). A cluster of eight workstations with two FPGA boards was built for this purpose. The algorithm is currently running as a pure software solution, but we are working to integrate the FPGAs in the computation. First results are encouraging, showing that the performance of the new platform can be high compared to pure software solutions