• DocumentCode
    3244254
  • Title

    Slipstream execution mode for CMP-based multiprocessors

  • Author

    Ibrahim, Khaled Z. ; Byrd, Gregory T. ; Rotenberg, Eric

  • Author_Institution
    Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
  • fYear
    2003
  • fDate
    8-12 Feb. 2003
  • Firstpage
    179
  • Lastpage
    190
  • Abstract
    Scalability of applications on distributed shared-memory (DSM) multiprocessors is limited by communication overheads. At some point, using more processors to increase parallelism yields diminishing returns or even degrades performance. When increasing concurrency is futile, we propose an additional mode of execution, called slipstream mode, that instead enlists extra processors to assist parallel tasks by reducing perceived overheads. We consider DSM multiprocessors built from dual-processor chip multiprocessor (CMP) nodes with shared L2 cache. A task is allocated on one processor of each CMP node. The other processor of each node executes a reduced version of the same task. The reduced version skips shared-memory stores and synchronization, running ahead of the true task. Even with the skipped operations, the reduced task makes accurate forward progress and generates an accurate reference stream, because branches and addresses depend primarily on private data. Slipstream execution mode yields two benefits. First, the reduced task prefetches data on behalf of the true task. Second, reduced tasks provide a detailed picture of future reference behavior, enabling a number of optimizations aimed at accelerating coherence events, e.g., self-invalidation. For multiprocessor systems with up to 16 CMP nodes, slipstream mode outperforms running one or two conventional tasks per CMP in 7 out of 9 parallel scientific benchmarks. Slipstream mode is 12-19% faster with prefetching only and up to 29% faster with self-invalidation enabled.
  • Keywords
    cache storage; distributed shared memory systems; performance evaluation; CMP-based multiprocessors; DSM multiprocessors; accurate reference stream; application scalability; coherence event acceleration; distributed shared-memory; dual-processor chip multiprocessor nodes; optimizations; parallel tasks; perceived overhead reduction; performance; prefetching; self-invalidation; shared L2 cache; skipped operations; slipstream execution mode; Acceleration; Character generation; Coherence; Concurrent computing; Degradation; Multiprocessing systems; Parallel processing; Performance gain; Prefetching; Scalability;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings. The Ninth International Symposium on
  • ISSN
    1530-0897
  • Print_ISBN
    0-7695-1871-0
  • Type

    conf

  • DOI
    10.1109/HPCA.2003.1183536
  • Filename
    1183536