• DocumentCode
    3244710
  • Title

    Automatic partitioning of signal processing programs for symmetric multiprocessors

  • Author

    Newburn, Chris J. ; Shen, John Paul

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    1996
  • fDate
    35339
  • Firstpage
    269
  • Lastpage
    280
  • Abstract
    Symmetric multiprocessor systems are increasingly common, not only as servers, but as a vehicle for executing a single application in parallel in order to reduce its execution latency. This paper presents PEDIGREE, a compilation tool that employs a new partitioning heuristic based on the program dependence graph (PDG). PEDIGREE creates overlapping inter-dependent threads, each executing on a subset of the SMP´s processors that marches the thread´s available parallelism. A unified framework is used to build threads from procedures, loop nests, loop iterations, and smaller constructs. PEDIGREE does not require any parallel language support; it is a post-compilation tool that reads in object code. The SDIO Signal and Data Processing Benchmark Suite has been selected as an example of real-time, latency-sensitive code. Its coarse-grained data flow parallelism is exploited by PEDIGREE to achieve speedups of 1.56x/2.11x (mean/max) and 1.61x/2.60x on two and four processors, respectively. There is roughly a 15% improvement over existing techniques that exploit only data parallelism. By exploiting the unidirectional flow of data for coarse-grained pipelining, the synchronization overhead is typically limited to less than 6% for synchronization latency of 100 cycles, and less than 2% for 10 cycles
  • Keywords
    multiprocessing systems; parallel architectures; program compilers; synchronisation; PEDIGREE; SDIO Signal and Data Processing Benchmark Suite; automatic partitioning; compilation tool; execution latency; loop iterations; loop nests; partitioning heuristic; post-compilation tool; program dependence graph; signal processing programs; symmetric multiprocessors; synchronization latency; synchronization overhead; Application software; CMOS technology; Data processing; Delay; Kernel; Parallel processing; Programming profession; Scheduling; Signal processing; Yarn;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Architectures and Compilation Techniques, 1996., Proceedings of the 1996 Conference on
  • Conference_Location
    Boston, MA
  • ISSN
    1089-795X
  • Print_ISBN
    0-8186-7633-7
  • Type

    conf

  • DOI
    10.1109/PACT.1996.552675
  • Filename
    552675