DocumentCode
3247827
Title
A 0.13 /spl mu/m 6 GHz 256/spl times/32b leakage-tolerant register file
Author
Krishnamurthy, R. ; Alvandpour, A. ; Balamurugan, G. ; Shanbhagh, N. ; Soumyanath, K. ; Borkar, S.
Author_Institution
Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA
fYear
2001
fDate
14-16 June 2001
Firstpage
25
Lastpage
26
Abstract
This paper describes a 256/spl times/32b 4-read, 4-write ported register file for 6 GHz operation in 1.2 V, 0.13 /spl mu/m technology. The local bitline uses a pseudo-static leakage tolerant scheme to achieve 8% faster read performance and 36% higher DC noise robustness (with 6/spl times/ active leakage reduction) compared to dual-Vt scheme optimized for high-performance.
Keywords
CMOS digital integrated circuits; VLSI; integrated circuit design; integrated circuit noise; leakage currents; microprocessor chips; 0.13 micron; 1.2 V; 32 bit; 6 GHz; CMOS; DC noise robustness; VLSI; active leakage reduction; leakage-tolerant register file; local bitline; microprocessor chips; ported register file; pseudo-static leakage tolerant scheme; Active noise reduction; CMOS technology; Circuit noise; Copper; Degradation; Delay; Microprocessors; Noise robustness; Registers; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2001. Digest of Technical Papers. 2001 Symposium on
Conference_Location
Kyoto, Japan
Print_ISBN
4-89114-014-3
Type
conf
DOI
10.1109/VLSIC.2001.934182
Filename
934182
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