• DocumentCode
    3248572
  • Title

    Explicit-enumeration based verification made memory-efficient

  • Author

    Nalumasu, Ratan ; Gopalakrishnan, Ganesh

  • Author_Institution
    Dept. of Comput. Sci., Utah Univ., Salt Lake City, UT, USA
  • fYear
    1995
  • fDate
    29 Aug-1 Sep 1995
  • Firstpage
    617
  • Lastpage
    622
  • Abstract
    We investigate new techniques for reducing the memory requirements of an on-the-fly model checking tool that employs explicit enumeration. Two techniques are studied in depth: exploiting symmetries in the model, and exploiting sequential regions in the model. These techniques can result in a significant reduction in memory requirements, and often find progress violations at much lower stack depths. Both techniques have been implemented as part of the SPIN verifier, a widely used on-the-fly model-checking tool
  • Keywords
    formal verification; logic CAD; logic testing; enumeration; enumeration based; memory requirements; on-the-fly model checking tool; verification; Cities and towns; Computer science; Contracts; Electronic mail; Explosions; Hardware; Protocols; Runtime; Software systems; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages. IFIP International Conference on Very Large Scal
  • Conference_Location
    Chiba
  • Print_ISBN
    4-930813-67-0
  • Type

    conf

  • DOI
    10.1109/ASPDAC.1995.486378
  • Filename
    486378