A novel technique for reducing leakage current of VLSI combinational circuits

In this paper, a new technique for reducing the leakage current of CMOS VLSI circuits is proposed. It makes use of the fact that leakage currents of gates are depended on their input patterns. The order of gate input lines is manipulated to reduce the leakage current. The key feature of the method, which reduces leakage current in both standby and active mode, is that it does not have any overhead on the area, dynamic power and the speed. Up to 20% of the static power reduction is achieved by applying this method to ISCAS85 benchmark circuits.