A 0.18 /spl mu/m high-performance logic technology

Author

Crowder, S. ; Greco, S. ; Ng, H. ; Barth, E. ; Beyer, K. ; Biery, G. ; Connolly, J. ; DeWan, C. ; Ferguson, R. ; Chen, X. ; Hargrove, M. ; Nowak, E. ; McLaughlin, P. ; Purtell, R. ; Logan, R. ; Oberschmidt, J. ; Ray, A. ; Ryan, D. ; Tallman, K. ; Wagner,

Author_Institution

IBM Semicond. Res. & Dev Center, Hopewell Junction, NY, USA

fYear

1999

fDate

14-16 June 1999

Firstpage

105

Lastpage

106

Abstract

In this paper, we describe a high-performance 0.18 /spl mu/m logic technology with dual damascene copper metallization and dense SRAM memory. Local interconnect technology allows us to fabricate SRAM cells as small as 3.84 /spl mu/m/sup 2/. We demonstrate that copper metallization continues to exhibit performance advantages over aluminum-based technologies in this generation.

Keywords

CMOS logic circuits; SRAM chips; copper; integrated circuit interconnections; integrated circuit measurement; integrated circuit metallisation; ultraviolet lithography; 0.18 micron; CMOS technology; Cu; NFET; PFET; SRAM cells; aluminum-based technologies; copper metallization; dense SRAM memory; dual damascene copper metallization; gate lithography; local interconnect technology; logic technology; Conductors; Copper; Delay; Integrated circuit interconnections; Isolation technology; Lithography; Logic; Metallization; Random access memory; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1999. Digest of Technical Papers. 1999 Symposium on

Conference_Location

Kyoto, Japan

Print_ISBN

4-930813-93-X

Type

conf

DOI

10.1109/VLSIT.1999.799362

Filename

799362