Power consumption awareness in cache memory design with SystemC

Author

Niar, Smail ; Meftali, Samy ; Dekeyser, Jean-Luc

Author_Institution

INRIA-FUTURS, Lille Univ., France

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

244

Lastpage

247

Abstract

This study presents the development of a cache memory module in a component library, designed for fast and synthetic embedded system simulation. This paper also demonstrates the possibility of integrating an existing power consumption analytical model in a SystemC description at the cycle-accurate register-transfer level (RTL).

Keywords

cache storage; electronic engineering computing; embedded systems; integrated circuit design; integrated memory circuits; power consumption; RTL; SystemC description; cache memory design; cache memory module; electronic engineering computing; embedded system simulation; power consumption analytical model; register transfer level; system-on-chip; Cache memory; Design methodology; Electronic packaging thermal management; Embedded system; Energy consumption; Hardware; Libraries; Mobile computing; Power system modeling; Thermal management;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics, 2004. ICM 2004 Proceedings. The 16th International Conference on

Print_ISBN

0-7803-8656-6

Type

conf

DOI

10.1109/ICM.2004.1434257

Filename

1434257

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3252045