Exploration of the Circuit Potential of Multiple-Gate Field-Effect Transistors

Author

Ramos, J. ; Nackaertsa, A. ; Chiarella, T. ; von Arnim, K. ; Varela, O. ; Augendre, E. ; Severi, S. ; Kerner, C. ; Rosmeulen, M. ; Hoffmann, T. ; Collaert, N. ; Jurczak, M. ; Biesemans, S.

Author_Institution

IMEC, Leuven

fYear

2006

fDate

2-5 Oct. 2006

Firstpage

167

Lastpage

168

Abstract

A comprehensive analysis of operational tall triple-gate MuGFET ring oscillators (ROs) is presented for the first time. Device geometries, process options and best inverter layout are discussed based on measured power and delay. A MOS model 11 based macro-model has been calibrated and correlated to hardware to enable a study on work-function tuning, conformal S/D extensions, strain engineering, raised S/D extensions and their impact at circuit level. Performance is benchmarked against reference bulk-planar LSTP and HP CMOS processes options to determine MuGFETs applicability opportunities. Finally, a new metric is used to assess CMOS technologies circuit potential, demonstrating the superior characteristics of MuGFET devices for low-power (LP) and for low-operational power (LOP) applications

Keywords

CMOS integrated circuits; MOSFET; low-power electronics; semiconductor device models; work function; CMOS technologies; MuGFET ring oscillators; multiple-gate field effect transistors; strain engineering; work-function tuning; CMOS technology; Circuits; Delay; FETs; Geometry; Hardware; Inverters; Power measurement; Ring oscillators; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

International SOI Conference, 2006 IEEE

Conference_Location

Niagara Falls, NY

ISSN

1078-621X

Print_ISBN

1-4244-0289-1

Electronic_ISBN

1078-621X

Type

conf

DOI

10.1109/SOI.2006.284490

Filename

4062938