Threshold-voltage anomaly in sub-0.2 μm DRAM buried-channel pFET devices

Measurements and simulation have been used to study threshold-voltage (V_t) dependence on gate oxide thickness (t _ox) for long-channel buried-channel (BC-) pFET devices in sub-0.2 μm CMOS technologies. The combination of the dual gate oxide process using N₂ implantation to create the thinner gate oxide and well RTA results in the thinner t_ox devices having higher V_t, contrary to expectation (V_t-t_ox anomaly). Detailed analysis of doping profiles, depletion contours, and electric potential confirms this anomaly both in the enhancement and depletion modes of operation. These studies show that a balance of net doping between that near the surface and that around the BC-layer is a stringent requirement for the Vt control in BC-pFETS