VLSI Architectures for Layered Decoding for Irregular LDPC Codes of WiMax

Author

Gunnam, K.K. ; Choi, G.S. ; Yeary, Mark B ; Atiquzzaman, M.

Author_Institution

Texas A&M Univ., College Station

fYear

2007

fDate

24-28 June 2007

Firstpage

4542

Lastpage

4547

Abstract

We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2times when compared to the recent state-of-the-art decoder architectures.

Keywords

VLSI; WiMax; block codes; decoding; message passing; parity check codes; scheduling; turbo codes; IEEE 802.16e WiMax standard; VLSI architecture; block-serial scheduling; irregular LDPC code; turbo decoding message passing algorithm; value-reuse property; Code standards; Computer architecture; Decoding; Message passing; Parity check codes; Processor scheduling; Scheduling algorithm; Throughput; Very large scale integration; WiMAX;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, 2007. ICC '07. IEEE International Conference on

Conference_Location

Glasgow

Print_ISBN

1-4244-0353-7

Type

conf

DOI

10.1109/ICC.2007.750

Filename

4289421

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3254573