MTNET: Design and Optimization of a Wireless SOC Test Framework

Author

Zhao, Dan ; Wang, Yi

Author_Institution

Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, Lafayette, LA

fYear

2006

fDate

24-27 Sept. 2006

Firstpage

239

Lastpage

242

Abstract

This paper focuses on a novel self-configurable multihop wireless on-chip micronetwork, namely MTNet, to serve as the test access architecture for testing next generation billion-transistor SoCs. A geographic routing algorithm is proposed to find the test access paths for deeply embedded cores. Further, a path driven test scheduling algorithm is developed to design and optimize the MTNet-based SoC test access architecture. Extensive simulation study show the feasibility and applicability of using MTNet for nanoscale SoC testing.

Keywords

circuit optimisation; embedded systems; integrated circuit design; integrated circuit testing; network routing; system-on-chip; MTNet; billion-transistor SoC testing; embedded cores; geographic routing algorithm; nanoscale SoC testing; path driven test scheduling algorithm; self-configurable multihop wireless on-chip micronetwork; test access architecture; wireless SoC test framework design; wireless SoC test framework optimization; Automatic testing; Communication system control; Costs; Design optimization; Integrated circuit interconnections; Integrated circuit technology; Job shop scheduling; Network-on-a-chip; Radio frequency; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

SOC Conference, 2006 IEEE International

Conference_Location

Taipei

Print_ISBN

0-7803-9781-9

Electronic_ISBN

0-7803-9782-7

Type

conf

DOI

10.1109/SOCC.2006.283889

Filename

4063058