Power simulation using test sets: An experimental analysis

It happens often that designers utilize test sets for power simulation. This choice has three advantages: First, test vectors can be easily generated by efficient ATPG tools. Second, the number of patterns included in test sets is usually limited; this implies short simulation times. Third, since test vectors tend to sensitize most of the internal nodes of a circuit, a good distribution of the samples considered for power analysis is guaranteed. Unfortunately, using test vectors for power simulation has a drawback: In normal operation mode, only the most common functionalities of a circuit are exercised. On the contrary, test sets tend to sensitize a larger number of behaviors; therefore, there may be cases in which estimation results are not very accurate. In this paper, we provide results of an experimental investigation we have carried out on the use of test sets for power simulation. We report comparative data for standard benchmark circuits; in addition, we consider a realistic case study for which input streams can be generated using RTL simulation