Analysis of a low power passive RFID tag based on advanced CMOS process for wide area application

Passive RFID application is often used in back scatter mode where a weak reflected signal is relied upon by reader systems. This limits the application of the technology as the reader and tag distance is constrained. This paper presents a passive design where planar capacitors are used to locally store charges to power a tag based on newer CMOS technology. In this paper BSIM4 transistor model based CMOS circuits are used to design a simple LFSR based RFID tag. A GHz clock is generated using inverter connected in series. As all the components, including the capacitors are all on one substrate, the circuit is essentially monolithic. The proposal has been modeled using an advanced ADS momentum tool. The storage capacitor has shown excellent ability to support the operation of the CMOS circuits due to the low power consumption, keeping the voltage level stable. The system assumes one antenna to capture and store power while an independent antenna to transmit the LFSR code.