• DocumentCode
    3256596
  • Title

    Design of a low swing power-efficient output stage for DC-DC converters

  • Author

    Lao, Jiahong ; Tan, Meng Tong

  • Author_Institution
    Sch. of Electr. & Electron. Eng., Nanyang Technol. Univ., Singapore, Singapore
  • fYear
    2009
  • fDate
    23-26 Jan. 2009
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    DC-DC converter is required to supply various DC voltage levels from battery to logic devices for most of the portable systems, such as cellular phone, portable DVD, CD player, etc. As the energy capacity of a battery is usually very limited, DC-DC converter with high efficiency over the entire load range is necessary to extend the battery life time. In this paper, a low swing gate controlled output stage design with capacitor charge recycling scheme is proposed to improve the light load efficiency. Theoretical calculation and Hspice simulation results prove that the proposed low swing output stage design significantly provides a maximum of 8% improvement in light load efficiency for a 3.6V-to-1.2V low power synchronous buck converter operating in 2MHz PWM CCM mode.
  • Keywords
    DC-DC power convertors; PWM power convertors; SPICE; power capacitors; DC-DC converters; Hspice simulation; capacitor charge recycling scheme; energy capacity; frequency 2 MHz; low power synchronous buck converter; low swing power-efficient output stage design; voltage 3.6 V to 1.2 V; Batteries; Buck converters; Capacitors; Cellular phones; DC-DC power converters; DVD; Lighting control; Logic devices; Recycling; Voltage; buck converter; charge recycling; component; light load; low swing; power efficiency;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    TENCON 2009 - 2009 IEEE Region 10 Conference
  • Conference_Location
    Singapore
  • Print_ISBN
    978-1-4244-4546-2
  • Electronic_ISBN
    978-1-4244-4547-9
  • Type

    conf

  • DOI
    10.1109/TENCON.2009.5396068
  • Filename
    5396068