• DocumentCode
    3257218
  • Title

    Two new techniques for compiled multi-delay logic simulation

  • Author

    Lee, Yun Sik ; Maurer, Peter M.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA
  • fYear
    1992
  • fDate
    8-12 Jun 1992
  • Firstpage
    420
  • Lastpage
    423
  • Abstract
    The authors describe two techniques for compiled event driven multidelay logic simulation that provide significant performance improvements over interpreted multidelay logic simulation. These two techniques are based on the concept of retargetable branch instructions that can be used to switch segments of code into and out of the instruction stream. The second algorithm, called the shadow technique, has been designed especially for systems with instruction caches. Benchmark experiments showed that these two techniques were up to 15 times faster than the interpreted multidelay simulator, with an average improvement of about five times for the fastest method
  • Keywords
    circuit analysis computing; delays; discrete event simulation; logic CAD; compiled multi-delay logic simulation; event driven multidelay logic simulation; instruction caches; instruction stream; retargetable branch instructions; shadow technique; Algorithm design and analysis; Circuit simulation; Computational modeling; Computer science; Computer simulation; Delay effects; Discrete event simulation; Logic; Switches; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
  • Conference_Location
    Anaheim, CA
  • ISSN
    0738-100X
  • Print_ISBN
    0-8186-2822-7
  • Type

    conf

  • DOI
    10.1109/DAC.1992.227767
  • Filename
    227767