TEMPT: technology mapping for the exploration of FPGA architectures with hard-wired connections

TEMPT is a technology mapping algorithm aimed at exploring field-programmable gate array (FPGA) architectures with hard-wired connections. TEMPT maps a network of basic blocks to a netlist of hard-wired logic blocks (HLBs), in which each HLB consists of several basic hard-wire blocks connected in an arbitrary tree topology, and optimizes either speed or area. TEMPT is as effective as the Xilinx 4000 CLB mapper, PPR, when minimizing CLBs to implement a set of MCNC benchmarks. Using TEMPT it was shown empirically that many HLBs were significantly faster than FPGAs without hard-wired links. Several HLBs were demonstrated that exhibited superior logic density to the Xilinx 4000 CLB