DocumentCode
3258780
Title
A graph theoretic technique to speed up floorplan area optimization
Author
Wang, Ting-Chi ; Wong, D.F.
Author_Institution
Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
fYear
1992
fDate
8-12 Jun 1992
Firstpage
62
Lastpage
68
Abstract
The authors present two algorithms to optimally select implementations for rectangular and L-shaped subfloorplans. The algorithms are designed specifically for the floorplan optimization algorithm given by T.-C. Wang and D.F. Wong (see Proc. 27th ACM/IEEE Des. Autom. Conf., p.180-6 (1990)), but they can also be applied to other algorithms as well. The experimental results, based on incorporating the two algorithms into Wang´s algorithm, whose performance was considerably improved were very encouraging. For the test runs where Wang´s algorithm failed to run, the algorithms helped to produce satisfactory solutions
Keywords
circuit layout CAD; graph theory; L-shaped subfloorplans; floorplan area optimization; graph theoretic technique; rectangular subfloorplans; test runs; Algorithm design and analysis; Design optimization; Polynomials; Shortest path problem; Testing; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-2822-7
Type
conf
DOI
10.1109/DAC.1992.227860
Filename
227860
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