SWiTEST: a switch level test generation system for CMOS combinational circuits

Author

Lee, K.J. ; Njinda, C.A. ; Breuer, M.A.

Author_Institution

Dept. of Electr. Eng., Nat. Cheng-Kung Univ., Tainan, Taiwan

fYear

1992

fDate

8-12 Jun 1992

Firstpage

26

Lastpage

29

Abstract

The authors present a switch level test generation system called SWiTEST. SWiTEST deals with bridging, breaking, stuck-open/on and stuck-at-faults. It employs both logic and current monitoring and takes into account the invalidation problem associated with stuck-open tests. The framework for SWiTEST is based on the PODEM algorithm. Some experimental results are presented and discussed. The experimental results imply that switch level test generation can be done in CPU time that is within an order of magnitude of that required for gate level test generation

Keywords

CMOS integrated circuits; combinatorial circuits; fault location; logic testing; CMOS combinational circuits; PODEM algorithm; SWiTEST; breaking; bridging; current monitoring; gate level test generation; stuck-at-faults; stuck-open; switch level test generation system; CMOS logic circuits; Circuit faults; Circuit testing; Combinational circuits; Logic testing; Monitoring; Semiconductor device modeling; Switches; Switching circuits; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1992. Proceedings., 29th ACM/IEEE

Conference_Location

Anaheim, CA

ISSN

0738-100X

Print_ISBN

0-8186-2822-7

Type

conf

DOI

10.1109/DAC.1992.227868

Filename

227868