DocumentCode
3259638
Title
A novel 8T SRAM cell with improved read-SNM
Author
Sil, Abhijit ; Ghosh, Soumik ; Bayoumi, Magdy
Author_Institution
Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, Lafayette, LA
fYear
2007
fDate
5-8 Aug. 2007
Firstpage
1289
Lastpage
1292
Abstract
As the MOSFET´s channel length is scaling down, SRAM stability becomes the major concern for future technology. The cell becomes more susceptible to both process induced variation in device geometry and threshold voltage variability due to dopant fluctuation in the channel region. In this paper, a novel highly stable 8T SRAM cell is proposed which eliminate any noise induction during read operation and keep the read SNM as high as 468 mV at VDD = 1.2 V in 120 nm technology. The cell also supports low power operation at cell VDD as low as 0.34 V.This new asymmetric cell structure is capable of using differential sense technique for high speed read operation.
Keywords
MOSFET; SRAM chips; circuit stability; 8T SRAM cell; MOSFET channel length; SRAM stability; asymmetric cell structure; device geometry; read-SNM; threshold voltage; Energy consumption; Fluctuations; Geometry; Inverters; MOSFET circuits; Manufacturing processes; Noise reduction; Random access memory; Stability; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2007. NEWCAS 2007. IEEE Northeast Workshop on
Conference_Location
Montreal, Que
Print_ISBN
978-1-4244-1163-4
Electronic_ISBN
978-1-4244-1164-1
Type
conf
DOI
10.1109/NEWCAS.2007.4488015
Filename
4488015
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