DocumentCode
3259756
Title
Improving routing efficiency for network-on-chip through contention-aware input selection
Author
Wu, Dong ; Al-Hashimi, Bashir M. ; Schmitz, Marcus T.
Author_Institution
Sch. of Electron. & Comput. Sci., Southampton Univ.
fYear
2006
fDate
24-27 Jan. 2006
Abstract
The performance of network-on-chip (NoC) largely depends on the underlying routing techniques, which have two constituencies: output selection and input selection. Previous research on routing techniques for NoC has focused on the improvement of output selection. This paper investigates the impact of input selection, and presents a novel contention-aware input selection (CAIS) technique for NoC that improves the routing efficiency. When there are contentions of multiple input channels competing for the same output channel, CAIS decides which input channel obtains the access depending on the contention level of the upstream switches, which in turn removes possible network congestion. Simulation results with different synthetic and real-life traffic patterns show that, when combined with either deterministic or adaptive output selection, CAIS achieves significant better performance than the traditional first-come-first-served (FCFS) input selection, with low hardware overhead (<3%)
Keywords
integrated circuit layout; microprocessor chips; network routing; network-on-chip; CAIS technique; NoC; contention-aware input selection; multiple input channels; network routing; network-on-chip; output selection technique; routing efficiency; Communication switching; Computer aided instruction; Hardware; Network-on-a-chip; Packet switching; Routing; Switches; System-on-a-chip; Telecommunication traffic; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation, 2006. Asia and South Pacific Conference on
Conference_Location
Yokohama
Print_ISBN
0-7803-9451-8
Type
conf
DOI
10.1109/ASPDAC.2006.1594642
Filename
1594642
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