Hardware implementation of super minimum all digital FM demodulator

Author

Rahmatullah, Nursani ; Nugroho, Arif E.

Author_Institution

Dept. of Electr. Eng., Inst. Teknologi Bandung, Indonesia

fYear

2006

fDate

24-27 Jan. 2006

Abstract

We propose improvement of the new architecture of digital FM demodulator. This work enhances signal quality, system clock frequency, and superior than well known PLL technique today. No more multiplier, no more ROM or table, compact size, and very fast in transient or state response. Real implementation in Altera® APEX20K200 EBC652-1X PLD gives 348 logic elements and run up to 224.42 MHz.

Keywords

demodulators; digital signal processing chips; frequency modulation; Altera APEX20K200; EBC652-1X PLD; digital FM demodulator; logic elements; signal quality; state response; system clock frequency; transient response; Clocks; Demodulation; Electronic mail; Finite impulse response filter; Frequency modulation; Hardware; Phase locked loops; Read only memory; Signal processing; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation, 2006. Asia and South Pacific Conference on

Print_ISBN

0-7803-9451-8

Type

conf

DOI

10.1109/ASPDAC.2006.1594663

Filename

1594663

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3260172