An algorithm for standard-cell and gate array placement

In this paper the authors present an algorithm for standard-cell and gate array placement. This algorithm has been implemented as a part of TOPS-a layout synthesis package developed in the Institute of Informatics Systems. A new heuristics for standard cell placement was proposed that combines the features of iterative improvement with the ability to avoid getting stuck at local minima using a stochastic approach. The authors´ objective was to prevent the program from trapping at local minima on the one hand and on the other to reduce CPU-time compared with simulated annealing