Spec-based flip-flop and latch repeater planning

Shrinking process geometries and frequency scaling give rise to an increasing number of interconnects that require multiple clock cycles. This paper explores efficient techniques to insert flip-flops and latches to meet pre-determined latency and margin constraints at the receivers. Previous approaches push timing margins to either ends of interconnect. We present an O(n log n)-time algorithm to insert flip-flops that evens out timing margins across the entire interconnect, resulting in more robust designs and faster design convergence. An O(n log n)-time extension to handle symmetric, two-phases latches is also presented. Experimental results verify the correctness and practicality of our approach