Delay variation tolerance for domino circuits

Factors of delay variation, such as process variation and noise effects, may cause a manufactured chip to violate the pre-specified timing constraint. In this paper, we propose a re-synthesis technique to tolerate delay variation for domino circuits. Note that the slacks of nodes along critical paths are zero; any delay addition to those zero-slack nodes worsens the final performance of a circuit. Our basic idea is to increase the slacks of nodes in the critical region by appending a redundant auxiliary subcircuit to the original circuit. The auxiliary subcircuit can cause critical paths to become false paths or imperceptible paths as stated in S. Raj et al. (2004) so as to improve the capability of delay variation tolerance. Experimental results are very encouraging.